Exploring Optimal Topology and Routing Algorithm for 3D Network on Chip | Science Publications

American Journal of Applied Sciences

N. Viswanathan¹  K. Somasundaram¹  K. Paramasivam¹ 

关键词: SoC;    3D NoC;    3D topology;    TSVs;    IP blocks;    traffic rate;    buffer size;    network diameter;   

DOI  :  10.3844/ajassp.2012.300.308

学科分类：自然科学（综合）

来源: Science Publications

【 摘 要 】

Problem statement: Network on Chip (NoC) is an appropriate candidate to implement interconnections in SoCs. Increase in number of IP blocks in 2D NoC will lead to increase in chip area, global interconnect, length of the communication channel, number of hops transversed by a packet, latency and difficulty in clock distribution. 3D NoC is evolved to overcome the drawbacks of 2D NoC. Topology, switching mechanism and routing algorithm are major area of 3D NoC research. In this study, three topologies (3D-MT, 3D-ST and 3D-RNT) and routing algorithm for 3D NoC are presented. Approach: Experiment is conducted to evaluate the performance of the topologies and routing algorithm. Evaluation parameters are latency, probability and network diameter and energy dissipation. Results: It is demonstrated by a comparison of experimental results analysis that 3D-RNT is a suitable candidate for 3D NoC topology. Conclusion: TThe performance of the topologies androuting algorithm for 3D NoC is analysed. 3D-MT is not a suitable candidate for 3D NoC, 3D-ST is asuitable candidate provided interlayer communications are frequent and 3D-RNT is a suitablecandidate as interlayer communications are limited.

【 授权许可】

Unknown