The aggressive evolution of the semiconductor industrysmaller process geometries, higher densities, and greater chip complexityhas provided design engineers the means to create complex, high-performance System-on-a-Chip (SoC) designs.Such SoC designs typically have more than one processor and huge (tens of Mega Bytes) amount of memory, all on the same chip.Dealing with the global on-chip memory allocation/deallocation in a dynamic yet deterministic way is an important issue for upcoming billion transistor multiprocessor SoC designs.To achieve this, we propose a memory management hierarchy we call Two-Level Memory Management.To implement this memory management schemewhich presents a shift in the way designers look at on-chip dynamic memory allocationwe present the System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) for allocation of the global on-chip memory, which we refer to as Level Two memory management (Level One is the management of memory allocated to a particular on-chip Processing Element, e.g., an operating systems management of memory allocated to a particular processor).In this way, processing elements (heterogeneous or non-heterogeneous hardware or software) in an SoC can request and be granted portions of the global memory in a fast and deterministic time.A new tool is introduced to generate a custom optimized version of the SoCDMMU hardware. Also, a real-time operating system is modified support the new proposed SoCDMMU.We show an example where shared memory multiprocessor SoC that employs the Two-Level Memory Management and utilizes the SoCDMMU has an overall average speedup in application transition time as well as normal execution time.
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Dynamic Memory Management for Embedded Real-TimeMultiprocessor System-on-a-Chip