A 5-Gbit/s CDR circuit with 1.4 mW multi-PFD phase rotating PLL

IEICE Electronics Express

Kyoung-Ho Kim²  Kee-Won Kwon²  Jun-Han Bae²  Young-Hyun Jun¹ 

[1] Memory Division, Samsung Electronics Co.;College of Information & Communication Engineering, Sungkyunkwan University

关键词: clock and data recovery (CDR);    phase-rotating PLL;    jitter characteristics;    split-tuned architecture;   

DOI  :  10.1587/elex.11.20140828

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(11)With a new phase-rotating phase locked loop (RPLL), a 5-Gbit/s quarter-rate clock and data recovery (CDR) circuit is presented in this brief. The RPLL employs a split-tuned architecture to decouple the tradeoff between RPLL bandwidth and power consumption. The uncertainty of phase interpolation due to the non-deterministic characteristics of the phase frequency detector (PFD) is eliminated by employing a PFD synchronizer (PFDS). Hence RPLL precisely performs seamless phase adjustment. The CDR, implemented in a digital 65 nm CMOS technology, shows 5.5-ps rms and 47.2-ps peak-to-peak jitter in the recovered clock and 10�?12 bit error rate while consuming 10.3 mW from a 1.2-V supply.

【 授权许可】

Unknown