A 1.5�?5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

IEICE Electronics Express

Changsik Yoo¹  Dong-Ho Choi¹ 

[1] Department of Electronics & Computer Engineering, Hanyang University

关键词: clock and data recovery (CDR);    wireline transceiver;    phase locked loop (PLL);    phase rotation;    CMOS;   

DOI  :  10.1587/elex.11.20140351

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(17)A clock and data recovery (CDR) circuit for 1.5�?5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10�?12.

【 授权许可】

Unknown