A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection

IEICE Electronics Express

Taek-Joon Ahn¹  Yong-Sung Ahn¹  Kyung-Sub Son¹  Jin-Ku Kang¹ 

[1] Dept. of electronics Engineering, Inha University

关键词: clock and data recovery (CDR);    dynamic CML latch;    half-rate linear phase detector (PD);    V/I converter;   

DOI  :  10.1587/elex.11.20140657

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(3)A low-power clock and data recovery (CDR) circuit using dynamic current-mode logic (CML) latches followed by a V/I (Voltage to Current) converter merged with XOR for half-rate linear phase detection is described. The loop latency of the CDR is also reduced with the proposed scheme. Thus the faster locking time and jitter reduction could be achieved compared to the CDR using conventional static CML latches and XOR gates in a linear phase detector (PD) followed by a V/I converter. A CDR circuit with the proposed circuit topology has been designed and fabricated with 0.18-µm CMOS technology and has shown 5-Gb/s data recovery with 14.9 mW power saving compared to the conventional CDR structure under a 1.8-V supply

【 授权许可】

Unknown