Stacked-FET linear SOI CMOS SPDT antenna switch with input P1dB greater than 40dBm

IEICE Electronics Express

Donggu Im¹  Kwyro Lee¹ 

[1] Department of EE, Korea Advanced Institute of Science and Technology (KAIST)

关键词: antenna switch;    leakage current;    power handling capability;    SOI CMOS;    SPDT switch;   

DOI  :  10.1587/elex.9.1813

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(4)Cited-By(2)The power handling capability is the most stringent specification for antenna switches, and this is dominated by a significant amount of leakage current of off-state FETs. For achieving maximum power handling capability of antenna switches, new DC I-V (FFI-V) characterization method to characterize RF P1dB point of off-state FETs is proposed and experimental study on optimum DC gate and body bias is performed based on proposed FFI-V method. Using Ron and Coff of minimum channel length MOSFETs at aforementioned optimum DC bias point, antenna switch design methodology for maximum power handling capability and minimum insertion loss is established. The designed SOI CMOS SPDT antenna switch integrated with switch controller shows insertion loss less than 0.5dB and input P1dB greater than +40dBm.

【 授权许可】

Unknown