Leakage power reduction using the body bias and pin reordering technique

IEICE Electronics Express

Chien-Yi Roger Chen¹  Jae Woong Chun² 

[1] Department of Electrical Engineering and Computer Science, Syracuse University;Department of Electrical and Electronic Engineering, Anyang University

关键词: leakage current;    reverse/forward body bias;    pin reordering;    leakage power saving;    nanometer-scale CMOS circuits;   

DOI  :  10.1587/elex.13.20151052

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(10)Cited-By(1)This paper presents a new method to reduce the standby leakage power consumption using the body bias and pin reordering technique for nanometer-scale CMOS circuits. The proposed method, unlike the conventional reverse body biasing (RBB) technique, considers gate leakage to minimize the negative effects of the existing RBB approach. This minimization of the negative effects can be achieved by intelligently applying proper body bias to the appropriate CMOS network based on its status (on-/off-state) with the aid of a pin reordering technique. Experimental results on ISCAS�?85 benchmark circuits show that the proposed method can achieve improvements in terms of leakage power savings that range from 16% to 38% when compared with the previous works.

【 授权许可】

Unknown