Standby power reduction using optimal supply voltage and body-bias voltage

IEICE Electronics Express

Kyung Ki Kim¹  Yong-Bin Kim¹ 

[1] Department of Electrical and Computer Engineering, Northeastern University

关键词: leakage current;    standby power;    optimal supply voltage and body-bias voltage;    nanometer CMOS circuits;   

DOI  :  10.1587/elex.5.556

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)Cited-By(3)This paper proposes a novel design method to minimize the leakage power during standby mode using a novel optimal supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The minimum level of VDD is generated for different temperature and process conditions adaptively using a look-up-table method. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power by 1000 times on average for ISCAS85 benchmark circuits designed using 32nm CMOS technology comparing to the case where the method is not applied.

【 授权许可】

Unknown