Silicon-germanium BiCMOS and silicon-on-insulator CMOS analog circuits for extreme environment applications

Extreme environment;SOI CMOS;SiGe BiCMOS;Analog;Radiation;Microelectronics

England, Troy Daniel ; Cressler, John D. Electrical and Computer Engineering Hassler, Jennifer O. Durgin, Gregory D. Wang, Hua Hertel, Nolan E. ; Cressler, John D.

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Extreme environment;    SOI CMOS;    SiGe BiCMOS;    Analog;    Radiation;    Microelectronics;   

Others  :  https://smartech.gatech.edu/bitstream/1853/51806/1/ENGLAND-DISSERTATION-2014.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

Extreme environments pose major obstacles for electronics in the form of extremely wide temperature ranges and hazardous radiation. The most common mitigation procedures involve extensive shielding and temperature control or complete displacement from the environment with high costs in weight, power, volume, and performance. There has been a shift away from these solutions and towards distributed, in-environment electronic systems. However, for this methodology to be viable, the requirements of heavy radiation shielding and temperature control have to be lessened or eliminated. This work gained new understanding of the best practices in analog circuit design for extreme environments. Major accomplishments included the over-temperature -180 C to +120 C and radiation validation of the SiGe Remote Electronics Unit, a first of its kind, 16 channel, sensor interface for unshielded operation in the Lunar environment, the design of two wide-temperature (-180 C to +120 C), total-ionizing-dose hardened, wireline transceivers for the Lunar environment, the low-frequency-noise characterization of a second-generation BiCMOS process from 300 K down to 90 K, the explanation of the physical mechanisms behind the single-event transient response of cascode structures in a 45 nm, SOI, radio-frequency, CMOS technology, the analysis of the single-event transient response of differential structures in a 32 nm, SOI, RF, CMOS technology, and the prediction of scaling trends of single-event effects in SOI CMOS technologies.