A low-jitter pulsewidth control loop with high supply noise rejection

IEICE Electronics Express

Zhangming Zhu¹  Huaxi Gu²  Shubin Liu¹  Yintang Yang¹ 

[1] School of Microelectronics, Xidian University;School of Telecommunications Engineering, Xidian University

关键词: PWCL;    low-jitter;    noise rejection;    voltage substractor;    DCC;   

DOI  :  10.1587/elex.10.20130619

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(5)A low-jitter pulsewidth control loop (PWCL) with high supply noise rejection for high-speed pipelined ADC is presented in this letter. Based on the edge triggered PWCL, An improved charge pump, a novel control stage (CS) and delay compensation circuits (DCC) was utilized to decrease the supply-induced jitter. The experimental results demonstrate that within 180ns the PWCL can lock the clock duty cycles for the accuracy of 50±1% with 10%∼90% input duty cycle from 50MHz to 500MHz. The p-p jitter is 10.1ps at 500MHz, and the variation of duty cycle is less than 0.05% within ±10% supply noise.

【 授权许可】

Unknown