A fast-locking low-jitter pulsewidth control loop for high-speed pipelined ADC

IEICE Electronics Express

Zhangming Zhu¹  Huaxi Gu²  Lianxi Liu¹  Guangwen Yu¹  Yintang Yang¹  Jingyu Wang¹ 

[1] School of Microelectronics, Xidian University;School of Telecommunications Engineering, Xidian University

关键词: pipelined ADC;    PWCL;    fast-locking;    low-jitter;   

DOI  :  10.1587/elex.9.1237

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 授权许可】

Unknown