A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

IEICE Electronics Express

Liyuan Liu¹  Peng Feng¹  Zhao Zhang¹  Jian Liu¹  Nanjian Wu¹  Jincheng Yang¹ 

[1] State Key Laboratory of Super-Lattice and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, University of Chinese Academy of Sciences

关键词: self-biased PLL;    low-jitter;    wideband;    source-degeneration;    voltage-to-current converter;    multi-rate serial link transmitter;   

DOI  :  10.1587/elex.14.20170422

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This paper proposes wideband low-power low-jitter self-biased phase-locked loop (SBPLL) for multi-rate serial link transmitter application. It adopts a proposed low-power source-degeneration voltage-to-current converter not only to save power but also to reduce the phase noise contributed by the voltage-to-current converter. The proposed SBPLL is implemented in a 65-nm CMOS process, and the active core area is 0.01 mm2. Measurement result shows that the SBPLL can generate clock with frequency from 1.25 to 6.25 GHz and the loop bandwidth can be kept around 20 MHz regardless of the output frequency. The rms jitter integrated from 10 kHz to 300 MHz is 780 fs at carrier frequency of 6.25 GHz and maximum power efficiency is 0.496 mW/GHz with 1.2-V supply. The figure-of-merit (FOM) is −237.2 dB. The measurement results also show good robustness of the SBPLL over temperature and supply voltage variation.

【 授权许可】

CC BY