A 250KS/s, 0.8V ultra low power successive approximation register ADC using a Dynamic rail-to-rail comparator

IEICE Electronics Express

Huazhong Yang¹  Sekedi B. Kobenge¹ 

[1] Electronic Engineering Department, TNLIST, Tsinghua University

关键词: rail-to-rail comparator;    sample-and-hold;    digital-to-analog converter;    analog-to-digital converter;   

DOI  :  10.1587/elex.7.261

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)Cited-By(3)A low voltage low power successive approximation register (SAR) analog-to-digital converter (ADC) based on a novel rail-to-rail comparator is proposed in this paper. The power consumption of the comparator is significantly reduced through dynamic operation while the speed is augmented by using an efficient regenerative latch. No biasing circuits are needed and there are no floating nodes in the comparator throughout the conversion process. The digital-to-analog converter (DAC) is formed from a binary array of MIM capacitors. The 250KS/s ADC implemented in a 0.18µm process consumes only 1.35µW of power at a supply voltage of 0.8V.

【 授权许可】

Unknown