0.3–4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate

IEICE Electronics Express

Yuepeng Yan¹  Jingyu Han¹  Qiangtao Lai¹  Yulin Zhang¹  Hua Chen¹  Guiliang Guo² 

[1] Institute of Microelectronics, Chinese Academy of Sciences;University of Chinese Academy of Sciences

关键词: frequency divider;    divide-by-1.5;    wideband;    CML;    CMOS;   

DOI  :  10.1587/elex.14.20170450

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

An ultra-wideband differential divide-by-1.5 divider based on current-mode logic (CML) is proposed. It consists of a divide-by-3 circuit and an optimized CML-XOR gate. Fully symmetric and differential structure is proposed to extend upper bound working frequency. In the CML-XOR gate, two identical Gilbert cells with optimized eight-input signals are developed to strengthen the pull-down force, which benefits the high-speed division. Fabricated in TSMC 180 nm CMOS process, this divider achieves an operating frequency of 0.3–4.4 GHz for 0 dBm input, and consumes 4.14 mW from 1.8 V supply. The chip size is 0.02 mm2.

【 授权许可】

CC BY