High Performance and Low Leakage 3DSOI Fin-FET SRAM

American journal of engineering and applied sciences

Sudha, D.¹ 

关键词: Non Planner Devices;    SOI;    Ultra Low Voltage;    FINFET;    TCAD;    SRAM;   

DOI  :  10.3844/ajeassp.2017.101.107

学科分类：工程和技术（综合）

来源: Science Publications

【 摘 要 】

In recent semiconductor designs, the major key factors: Competent device simulations, precise device characterization, well power optimization, new architectural design and cost-effective fabrication drives the designers attention towards multi gate transistors as an alternative to MOSFET. Non planner device structures are a competitive edge over planner devices. Silicon-on-Insulator (SOI) FinFETs are hopeful among variety of multi-gate structures as they have simple fabrication, Superior gate control, lower subthreshold leakage and minimized susceptibility to process variations. Low leakage memory cells play a significant role of power consumption in the recent VLSI Systems. In this study, Ultra-low Voltage Asymmetric Short Gate (UVASG) FinFET is modeled with TCAD tools for low leakages and FinFET based SRAM has been proposed as a substitute for the bulk devices.

【 授权许可】

CC BY