Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

ETRI Journal

关键词: shielded metal line;    refresh time;    planar cell;    noise margin;    DRAM;   

Others  :  1184953
DOI  :  10.4218/etrij.04.0103.0140

【 摘 要 】

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of 3.63 µm2. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when Vcc is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

   

【 参考文献 】

• [1]Y.H. Park, S.H. Han, J.H. Lee, and H.J. Yoo, "A 7.1 GB/s Low-Power Rendering Engine in 2D Array Embedded Memory Logic CMOS for Portable Multimedia System," IEEE J. Solid-State Circuits, vol.36, 2001, pp. 944-955.
• [2]W. Kim, "A Platform-Based SoC Design of a 32-Bit Smart Card," ETRI J., vol. 25, no. 6, Dec. 2003, pp.510-516.
• [3]S. Lee, "Pipelined Macroblock Processing to Reduce Internal Buffer Size of Motion Estimation in Multimedia SoCs," ETRI J., vol. 25, no. 5, Oct. 2003, pp.297-304.
• [4]D.H. Suh and J.H. Lee, "A Process Technology for 0.16μm Embedded DRAM with Fast Logic Speed and Small DRAM Cell," J. Electrochem. Soc., vol. 151, 2004, pp. G618-622.
• [5]Y.J. Kim, J.H. Lee, Y.C. Jeong, and J.H. Cho, "Investigation of a Relationship between Refresh Time and Implantation Overlap in Capacitor Region of P-MOS DRAM Cell," Microelectronic Eng., vol. 71, 2004, pp. 262-265.
• [6]D.H. Suh, J.H. Cho, Y.C. Jeong, S.Y. Chi, J.G. Park, Y.J. Kim, and J.H. Lee, "Characterization of 3 Dimensional Capacitor Prepared by Oxide Recess in Shallow Trench Isolation," J. Electrochem. Soc., (in press).
• [7]Dong-Sun Min and Dietrich W. Langer, Senior Member, IEEE, "Multiple Twisted Dataline Techniques for Multigigabit DRAM’s," IEEE J. Solid-State Circuits, vol. 34, 1999, pp. 856-865.
• [8]H. Hidaka, F. Fujishima, Y. Matsuda, M. Asakura, and T. Yoshihara, "Twisted Bit-Line Architecture for Multi-Megabit DRAM’s," IEEE J.Solid-State Circuits, vol. 24, 1989, pp. 21-28.
• [9]M. Aoki, M. Horiguchi, and K. Itoh, "An Experimental 16-Mbit DRAM with Transposed Data Line Structure," ISSCC Dig. Tech. Papers, 1998, pp. 250-251.
• [10]W. Leung and F. C. Hsu, "Method and Apparatus for Complete Hiding of the Refresh of a Semiconductor Memory," US Patent #5,999,474, 1999.
• [11]M. Hashimoto, K. Abe, and A. Seshadri, "An Embedded DRAM Module Using a Dual Sense Amplifier Architecture in a Logic Process," ISSCC Dig. Tech. Papers, 1997, pp. 64-65.