Improved dual sided doped memristor: modelling and applications

The Journal of Engineering

Komal Singh¹  Muhammad Khalid¹  Anup Shrivastava¹  Jawar Singh¹ 

[1]Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, India

关键词: electronic device;    dynamic hazards;    noise margin;    saturation length;    nonlinear ionic drift model;    memristor ratioed logic;    I–V characteristics;    active layers;    delay time;    dual sided doped memristor;    device structure;    logic gates;    circuit level simulation;    single active layer memristors;    SPICE model;    frequency response;    hybrid complementary metal oxide semiconductor memristive logic;   

DOI  :  10.1049/joe.2013.0265

学科分类：工程和技术（综合）

来源: IET

【 摘 要 】

Memristor as a novel and emerging electronic device having vast range of applications suffer from poor frequency response and saturation length. In this paper, the authors present a novel and an innovative device structure for the memristor with two active layers and its non-linear ionic drift model for an improved frequency response and saturation length. The authors investigated and compared the I–V characteristics for the proposed model with the conventional memristors and found better results in each case (different window functions) for the proposed dual sided doped memristor. For circuit level simulation, they developed a SPICE model of the proposed memristor and designed some logic gates based on hybrid complementary metal oxide semiconductor memristive logic (memristor ratioed logic). The proposed memristor yields improved results in terms of noise margin, delay time and dynamic hazards than that of the conventional memristors (single active layer memristors).

【 授权许可】

CC BY