Noise margin and short-circuit current in FGMOS logics

IEICE Electronics Express

Luis F. Cisneros-Sinencio¹  Jaime Ramirez-Angulo²  Alejandro Diaz-Sanchez¹ 

[1] National Institute for Astrophysics, Optics and Electronics;New Mexico State University

关键词: floating-gate logic;    noise margin;    FGMOS transistor;   

DOI  :  10.1587/elex.8.1967

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(10)Cited-By(2)Even when floating-gate logics are very-low-voltage circuits, as power supply is reduced, large fan-in FGMOS gates are prone to fail. Thus, determining the negative impact of noise margin and short-circuit current in this type of circuits is crucial to achieve optimal operation for a particular application. For this reason, a systematic and reliable technique for obtaining the correlation between fan-in and supply voltage, simultaneously considering noise margin and short-circuit current, is proposed.

【 授权许可】

Unknown