ETRI Journal | |
A Kernel-Based Partitioning Algorithm for Low-Power, Low-Area Overhead Circuit Design Using Don’t-Care Sets | |
关键词: don’t-care; logic optimization; partitioning; area optimization; Power optimization; | |
Others : 1184490 DOI : 10.4218/etrij.02.0202.0004 |
|
【 摘 要 】
This letter proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don’t-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don’t-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.
【 授权许可】
【 预 览 】
Files | Size | Format | View |
---|---|---|---|
20150520102752733.pdf | 207KB | download |
【 参考文献 】
- [1]M. Alidina, J. Monteiro, S. Devadas, and A. Ghosh, "Precomputation-Based Logic Optimization for Low Power,"Proc. ICCAD, Nov. 1994, pp. 74-81.
- [2]V. Tiwari, S. Malik, and P. Ashar, "Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 17, no. 10, Oct. 1998, pp. 1051-1060.
- [3]I.S. Choi and S.Y. Hwang, "A Circuit Partitioning Algorithm for Low Power Design under Area Constraints Using Simulated Annealing," IEE Proceedings - Circuits, Devices, and Systems, vol. 146, no. 1, Feb. 1999, pp. 8-15.
- [4]R. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. on Computers, vol. C-35, no. 8, Aug. 1986, pp. 677-691.
- [5]M. Damiani and De Micheli, "Don’t Care Set Specifications in Combinational and Synchronous Logic Circuits," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 12, no. 3, Mar. 1993, pp. 365-388.
- [6]A. Aziz, F. Balarin, R. Brayton, and A. Sangiovanni-Vincentelli, "Sequential Synthesis Using SIS," Proc. ICCAD, Nov. 1995, pp. 612-617.
- [7]C.-S. Yim, J.-S. Roh, E.-S. Choi, J.-H. Baek, and S.-J. Cho, "Resynchronization of Modified JPEG Using a Power Allocation Scheme in a Direct Sequence CDMA System," ETRI J., vol. 24, no. 5, Oct. 2002, pp. 405-408.
- [8]H.S. Lee, U.G. Joo, H.H. Lee, and W.W. Kim, "Optimal Time Slot Assignment Algorithm for Combined Unicast and Multicast Packets," ETRI J., vol. 24, no. 2, Apr. 2002, pp. 172-175.