Multimedia applications are currently prevalent for PCs and home entertainment. The user requirements are for ever increasing functionality and performance for ever decreasing cost. This tradeoff becomes even more critical in the arena of low cost embedded media appliances retailing for $300 or less. In this paper existing approaches to accelerating media algorithms for low cost systems are presented and their deficiencies highlighted. Further, the paper presents a novel approach to the acceleration of media algorithms for low cost embedded systems, by combining a small amount of FPGA with an embedded RISC processor, which provides the opportunity for fast turn-around of custom logic, for the acceleration of the algorithms, and furthermore provides programmable flexibility. The advantages provided by this approach relative to the existing approaches is highlighted. The utilisation of this small amount of FPGA requires careful partitioning of the algorithm into its hardware and software components. Two representative algorithms are presented and the partitioning criteria used for their mapping is detailed. Another critical aspect in achieving good performance improvement is the interaction between the CPU and the FPGA. Three different modes of interaction are presented and the tradeoffs provided by each are detailed. The paper concludes with the results of the investigation and shows that significant performance improvements (ranging from 12 to 21 times relative to the software implementation) is indeed possible using this approach. Future work in automating the analysis and partitioning of the algorithm, currently in progress, should further enhance the performance improvements and reduce the time to market of these systems.
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