Synthesis method of high speed finite state machines

Bulletin of the Polish Academy of Sciences. Technical Sciences

R. Czerwi?skiInstitute of Electronics, Silesian University of Technology, 16 Akademicka St., 44-100 Gliwice, PolandOther articles by this author:De Gruyter OnlineGoogle Scholar¹  D. KaniaInstitute of Electronics, Silesian University of Technology, 16 Akademicka St., 44-100 Gliwice, PolandOther articles by this author:De Gruyter OnlineGoogle Scholar¹ 

[1] Institute of Electronics, Silesian University of Technology, 16 Akademicka St., 44-100 Gliwice, Poland

关键词: Keywords: state assignment;    Finite State Machines (FSM);    Programmable Array Logic (PAL);    Complex Programmable Logic Devices (CPLD);    logic optimization;    tri-state buffer;   

DOI  :  10.2478/v10175-010-0067-6

学科分类：工程和技术（综合）

来源: Polska Akademia Nauk * Centrum Upowszechniania Nauki / Polish Academy of Sciences, Center for the Advancement of Science

【 摘 要 】

The paper is concerned with the problem of state assignment and logic optimization of high speed finite state machines. The method is designed for PAL-based CPLDs implementations. Determining the number of logic levels of the transition function before the state encoding process, and keeping the constraints during the process is the main problem at hand. A number of coding bits, as well as codes for the states, are adjusted to achieve a machine with a determined number of logic levels. Elements of two-level minimization are taken into consideration in the state assignment. The proposed optimization method is based on utilizing tri-state buffers, thus enabling achievement of a one-logic-level output block.

【 授权许可】

Unknown