Low Power Wallace Tree Encoder For Flash ADC

International Conference on Recent Advancements and Effectual Researches in Engineering Science and Technology

Ajanya, M.P.^1 ; Varghese, George Tom^2

Electronics and Communications Engineering, St. Josephs College of Engineering and Technology, Palai, Kerala, India^1

Dept. of ECE, St. Josephs College of Engineering and Technology, Palai, Kerala, India^2

关键词: Analog to digital converters;    CMOS technology;    Encoder circuits;    Mentor Graphics;    Parallel ADCs;    Resistor ladder;    Supply voltages;    Wallace tree;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/396/1/012042/pdf
DOI  :  10.1088/1757-899X/396/1/012042

来源: IOP

【 摘 要 】

Flash ADC is the fastest analog to digital converter. It is also known as parallel ADC. It consists of a resistor ladder, a comparator and an encoder circuit. The encoder circuit converts the thermometer code which is the output of comparator into binary code. The efficiency of encoder is very important. It should be capable of reducing the bubble errors and should dissipate low power. Wallace tree encoder is well efficient in reducing all the bubble errors. This paper proposes a low power Wallace tree encoder for Flash ADC. It is having a power dissipation of 939.43pW and delay of 5.38nS. The proposed encoder is implemented in 180nm CMOS technology with 1.8V supply voltage and was simulated using Mentor graphics.