FPGA design of the fast decoder for burst errors correction

International Conference on Information Technologies in Business and Industry 2016

计算机科学;经济学;工业技术

Mytsko, E.A.^1 ; Malchukov, A.N.^1 ; Zoev, I.V.^1 ; Ryzhova, S.E.^1 ; Kim, V.L.^1

Tomsk Polytechnic University, 30, Lenina Ave., Tomsk

634050, Russia^1

关键词: Burst errors;    Error correcting code;    FPGA design;    FPGA implementations;    Generator polynomial;    Module structure;    Single stage;    Without memory;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/803/1/012105/pdf
DOI  :  10.1088/1742-6596/803/1/012105

来源: IOP

【 摘 要 】

The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check-pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ∼20 ns.