Comparison of hardware and timing penalties for eliminating SRAM failures

2nd International Telecommunication Conference "Advanced Micro- and Nanoelectronic Systems and Technologies"

Shchigorev, L.A.^1^2 ; Shagurin, I.I.^1^2

National Research Nuclear University MEPhI, Moscow Engineering Physics Institute, Kashirskoe shosse 31, Moscow

115409, Russia^1

JSC 'Module', 3 Eight March 4th Street, Moscow

125190, Russia^2

关键词: Comparative analysis;    Error correcting code;    Fault-tolerant;    Hardware cost;    Memory access time;    Quantitative estimation;    Self-testing;    SRAM failures;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/498/1/012017/pdf
DOI  :  10.1088/1757-899X/498/1/012017

来源: IOP

【 摘 要 】

This article provides a quantitative estimation of timing and hardware penalties, which are the implication of different SRAM methods for failure elimination. Different ways of building fault-tolerant blocks of SRAM are discussed using error-correcting codes and self-testing - self-repair units. As criteria for evaluating hardware costs, the additional chip area required for the placement of fault tolerance is considered, the timing penalties are determined by the growth of memory access time. Comparative analysis of obtained results is made. It allows estimating the effectiveness of the considered methods of fault tolerance improvement.