Design Trade-off Between Performance and Fault-Tolerance of Space Onboard Computers

International Conference on Particle Physics and Astrophysics

物理学;天文学

Gorbunov, M.S.^1,2 ; Antonov, A.A.^1

Scientific Research Institute of System Analysis of Russian Academy of Sciences (SRISA), Nakhimovsky prospect 36-1, Moscow

117218, Russia^1

National Research Nuclear University MEPhI, Moscow Engineering Physics Institute, Kashirskoe highway 31, Moscow

115409, Russia^2

关键词: Chip areas;    Design tradeoff;    Error correcting code;    Memory design;    Multi-level cache;    Onboard computers;    Optimal solutions;    Trade off;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/798/1/012189/pdf
DOI  :  10.1088/1742-6596/798/1/012189

学科分类：天文学(综合)

来源: IOP

【 摘 要 】

It is well known that there is a trade-off between performance and power consumption in onboard computers. The fault-tolerance is another important factor affecting performance, chip area and power consumption. Involving special SRAM cells and error-correcting codes is often too expensive with relation to the performance needed. We discuss the possibility of finding the optimal solutions for modern onboard computer for scientific apparatus focusing on multi-level cache memory design.