Microarchitectural techniques to reduce energy consumption in the memory hierarchy

Energy;Cache;Dram;Microarchitecture

Ghosh, Mrinmoy ; Electrical and Computer Engineering

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Energy;    Cache;    Dram;    Microarchitecture;   

Others  :  https://smartech.gatech.edu/bitstream/1853/28265/1/ghosh_mrinmoy_200905_phd.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

This thesis states that dynamic profiling of the memory reference stream can improve energyand performance in the memory hierarchy. The research presented in this theses providesmultiple instances of using lightweight hardware structures to profile the memoryreference stream. The objective of this research is to develop microarchitectural techniquesto reduce energy consumption at different levels of the memory hierarchy. Several simpleand implementable techniques were developed as a part of this research. One of thetechniques identifies and eliminates redundant refresh operations in DRAM and reducesDRAM refresh power. Another, reduces leakage energy in L2 and higher level caches formultiprocessor systems. The emphasis of this research has been to develop several techniquesof obtaining energy savings in caches using a simple hardware structure called thecounting Bloom filter (CBF). CBFs have been used to predict L2 cache misses and obtainenergy savings by not accessing the L2 cache on a predicted miss. A simple extension ofthis technique allows CBFs to do way-estimation of set associative caches to reduce energyin cache lookups. Another technique using CBFs track addresses in a Virtual Cache andreduce false synonym lookups. Finally this thesis presents a technique to reduce dynamicpower consumption in level one caches using significance compression. The significantenergy and performance improvements demonstrated by the techniques presented in thisthesis suggest that this work will be of great value for designing memory hierarchies offuture computing platforms.