An integrated mapping table for hybrid FTL with fault-tolerant address cache

IEICE Electronics Express

Gi-Ho Park²  Seung-Ho Park¹  Shin-Dug Kim¹  Jung-Wook Park¹ 

[1] Supercomputing Lab., Dep. of Computer Science, Yonsei Univ.;Department of Computer Engineering, SeJong Univ.

关键词: NAND flash;    FTL;    Cache;   

DOI  :  10.1587/elex.6.368

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(8)Cited-By(1)Hybrid mapping technique is one of the most popular FTL (flash translation layer) mechanisms that perform flash address mapping efficiently. As the amount of flash storage grows, entire mapping tables for FTL cannot be loaded into the fast SRAM and physical page addresses are stored in the spare area. In such schemes, a page address cache is usually applied to decrease spare area searching time. However, significant amount of data information should be abandoned even if only a few cached addresses are lost by any power failure.The proposed method provides a table management scheme for hybrid mapping with its associated page address cache that can recover any lost data. Entire tables are integrated into the proposed map block, stored in a part of flash storage. The proposed table management scheme integrates various meta-data into a single hybrid map block which contains entire physical page table. The initial scan on this map block can generate various meta-data tables. Finally, the simulation results with general PC workload shows that, the proposed address cache shows miss rates below 1%.

【 授权许可】

Unknown