Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications

CMOS;VCO;Frequency dividers;Clock-data recovery;Phase-locked loops;Frequency synthesizers

Barale, Francesco ; Electrical and Computer Engineering

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: CMOS;    VCO;    Frequency dividers;    Clock-data recovery;    Phase-locked loops;    Frequency synthesizers;   

Others  :  https://smartech.gatech.edu/bitstream/1853/37216/1/barale_francesco_201012_phd.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply.The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a1 Vpower supply. The worst case phase noise is measured to be-80.1 dBc/Hz at1 MHzoffset from the highest frequency carrier(56.16 GHz). The output spectrum shows a reference spur attenuation of-32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming30 mWof power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.