Xilinx implementation of a serial-parallel digital converter

International Conference on Applied Sciences

自然科学（总论）

Cunan, C.D.^1 ; Baciu, I.^1 ; Dini, C.M.^1

Politehnica University of Timisoara, Department of Electrical Engineering and Industrial Informatics, 5 Revolution Street, Hunedoara

331128, Romania^1

关键词: Conversion process;    Digital converters;    Divider circuits;    Frequency dividers;    Output sequences;    Serial parallels;    Serial-parallel converter;    Synchronizing signal;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/477/1/012035/pdf
DOI  :  10.1088/1757-899X/477/1/012035

学科分类：自然科学（综合）

来源: IOP

【 摘 要 】

In the paper it is presented a serial parallel converter on 8 bit using a movement register with parallel output. The scheme created in Xilinx and implemented on a development board Nexis4DDr. The scheme contains two 4 bit counters and two registers schematically made and a frequency divider created in VHDL. The aimed sequence tact is obtained by dividing the tact frequency of 100MHz from the development board with the help of a divider circuit that allows the soft setup of the necessary frequency. The entering signal is brought to the serial input of a movement register, starting with the less significant bit. From the movement register the byte is transferred to the output register. The transfer between the two blocks is made in the moment when the 4 bits counter reaches 7 (moment which represents the closure of taking a bite) sequence which commands through a gate AND-NOT with three entrances, the command signal of the output data transfer. The output sequence can be memorized through a memorizing circuit or can be used for the command of a physical circuit. The H→L transition of the synchronizing signal, signal which is obtained also from the tact signal with the help of another 4 bit counter, determines the beginning of the conversion process. The circuit can function in a continuous way (without any reset circuit) or depending on the application it can be connected to a circuit which provides a command signal to obtain the reset signal of the implemented scheme.