Design of a High Resolution TDC Based on Multi-channel

2019 2nd International Conference on Advanced Materials, Intelligent Manufacturing and Automation

Zhang, Qingsong^1 ; Xu, Guanghui^1 ; Li, Na^1

College of Communication Engineering, Army University of Science and Technology, Nanjing, Jiangsu

210007, China^1

关键词: Digital converters;    Display modules;    Hardware resources;    High resolution;    High-precision;    Multi channel;    Non-linear error;    Nonlinear problems;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/569/3/032008/pdf
DOI  :  10.1088/1757-899X/569/3/032008

来源: IOP

【 摘 要 】

In this paper, a high precision time digital converter (TDC) system is designed based on Xilinx 7 series FPGA chip, which includes fine time measurement module, logic control module, rough count module and display module. The key point of FPGA TDC design is that there are a large number of delay units in the underlying hardware resources with stable delay. A delay chain consisting of 64 fast carry chains (CARRY4) is constructed by using the CARRY4 module inherent in the chip. In addition, the code density method is used to solve the nonlinear problem of internal special carry chain delay unit, effectively eliminate the error caused by wiring path, and reduce the integral nonlinear and differential nonlinear error. The experimental results show that the code density method can accurately reflect the distribution of delay time.