Design challenges and CAD solutions for low power and reliable monolithic 3D ICs

Monolithic;3D ICs;CAD;Thermal optimization;3D power delivery;Inter-tier variation;Power-performance-cost analysis

Samal, Sandeep Kumar ; Lim, Sung Kyu Electrical and Computer Engineering Raychowdhury, Arijit Mukhopadhyay, Saibal Naeemi, Azad J. Kim, Hyesoon ; Lim, Sung Kyu

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Monolithic;    3D ICs;    CAD;    Thermal optimization;    3D power delivery;    Inter-tier variation;    Power-performance-cost analysis;   

Others  :  https://smartech.gatech.edu/bitstream/1853/58245/1/SAMAL-DISSERTATION-2017.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

The major challenges in low power and reliable monolithic 3D IC design are studied and quantified. New CAD solutions are developed to address these challenges and obtain maximumbenefits from emerging monolithic 3D IC technology. The key design challenges in monolithic 3D ICs covered in this research include thermal modeling and optimization, 3D PDN design and analysis and addressing inter-tier performance difference and inter-tier interconnect difference. In addition, near-threshold voltage 3D IC design and analysis is also studied. A fast-accurate regression-based thermal modeling technique is developed for monolithic 3D ICs. This model is incorporated into a monolithic 3D IC floorplanner to make it thermal-aware. Thermal modeling and floorplanning is carried out for both conventional packages with heat sink and modern mobile packaging structure without any dedicated heat sink. Next, a detailed study is conducted to quantify the trade-off between signal and power routing unique to monolithic 3D ICs. Design optimization techniques are developed to minimize switching power overhead while satisfying power delivery constraints. The system level impact of low performance transistors in the top-tier of monolithic 3D ICs is quantified and new tier-aware gate-levelmonolithic 3D IC design flow is presented to enable low powerdesigns under practical settings. The adverse impact of BEOL in the bottom-tier of monolithic 3D ICs is also studied. New tier partitioning strategies are presented to mitigate performance degradation due to tungsten and to reduce congestion and metal layer usage in the bottom tier. Lastly, a power-performance-cost analysis of monolithic 3D ICs is presented using realistic cost data. Monolithic 3D IC benefits are also compared across different technology nodes. Overall impact of monolithic 3D IC technology is compared with 2D ICs and through-silicon-via (TSV)-based 3D ICs, and required design metrics and targets are estimated.