Physical design solutions for 3D ICs and their neuromorphic applications

Physical design solutions;3D ICs;Neuromorphic processor

Ku, Bon Woong ; Lim, Sung Kyu Electrical and Computer Engineering Mukhopadhyay, Saibal Raychowdhury, Arijit Krishna, Tushar Kim, Hyesoon ; Lim, Sung Kyu

University:Georgia Institute of Technology

Department:Electrical and Computer Engineering

关键词: Physical design solutions;    3D ICs;    Neuromorphic processor;   

Others  :  https://smartech.gatech.edu/bitstream/1853/61227/1/KU-DISSERTATION-2019.pdf

美国|英语

来源: SMARTech Repository

【 摘 要 】

The wafer-level 3D integration including face-to-face (F2F) and monolithic 3D (M3D) technologies has been featured as a promising innovation to succeed the horizontal device scaling benefit in the looming end of Moore’s law. While through-silicon-via-based 3D integration requires a huge silicon-area overhead to make 3D connections between separate tiers, the wafer-level 3D integration enables fine-grained vertical interconnections down tothe transistor-level. This allows physical designers the higher degrees of freedom in 3D placement and routing (P&R) than any other 3D integration approaches, which maximizes the power-performance-area (PPA) benefits of 3D ICs. The objective of this research is two-fold: Firstly, to develop computer-aided-design (CAD) methodologies to address potential issues of the wafer-level 3D integration includingpower integrity, inter-tier variations, and cost overhead. Secondly, to evaluate the PPA benefits of the wafer-level 3D integration to the neuromorphic processor design at the fullchip level by applying proposed solutions. For the first part, the static power integrity issue of transistor-level M3D ICs is inspected in detail, and we address the issue by proposing a new layout scheme for transistor-levelM3D standard cells. Next, physical design solutions for gate-level M3D ICs are developed to mitigate the negative impact of inter-tier device and interconnect variations, as well asthe cost overhead issue. In addition, we present the unique physical design solution named Compact-2D flow, which produces commercial-quality gate-level F2F IC layouts. For thesecond part, we adopt the liquid-state-machine architecture, a model of recurrent spiking neural networks, to build an online machine-learning hardware platform, and study thePPA benefits of gate-level F2F and M3D ICs on the non-trivial real-world speech recognition application. This work serves as an important step towards realizing bio-inspiredneuromorphic processors utilizing 3D IC design advantages.