Estimation-theoretic framework for robust and energy-efficient system design

Estimation theory for computation;robust system design;low-power design

Narayanan, Sriram

关键词: Estimation theory for computation;    robust system design;    low-power design;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/16057/Narayanan_Sriram.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

A fundamental hurdle to realizing the exciting future applications ofembedded computing is lack of adequate power supply. Unlike theexponential growth in computing capability, the improvements in powersources have been lackluster. Technology scaling, driven by Moore'slaw, has produced smaller devices that can operate on lower supplyvoltages; but as a side effect, nanoscale devices are becomingincreasingly unreliable.The resulting increase in transistor densityfurther exacerbates the power problem.Therefore, the computingindustry faces a pressing need to aggressively reduce powerconsumption and efficiently address error resiliency.Conventional approaches to error resiliency using redundantcomputations have incurred the associated overheads of power andsilicon area.Traditional power reduction techniques scale supplyvoltage or clock frequency to adapt to changing demands of theapplication, while being limited to ranges where computation is freeof error. Addressing in isolation the related problems of powerreduction and error tolerance may fail to produce the gains requiredby future systems. It may be desirable to allow occasional hardwareerrors for the sake of power savings; however, this trade-off must bedone without adversely impacting the end-user experience.Many applications in signal processing, communications, and multimediaalready allow several forms of noise, such as additive environmentalnoise, interference, and quantization. This research views hardwareerror as a new source of noise that is analogous to traditional formsof noise. In so doing, it enables dynamically trading-off reliabilityfor power savings while meeting application performance requirements.Our estimation-theoretic framework is a mathematical formalizationthat allows us to state system-on-chip (SoC) design problems asconstrained optimization problems. The engineering constraints, suchas hardware availability and cost, are explicitly captured as designconstraints. By accounting for application-level performancerequirements, the framework provides a notion of power, reliability,and performance optimality of the design. The mathematical abstractionof the framework results in different particular design techniquesdepending on the nature of the application. We have identified fourclasses on the basis of these design techniques, and describedapplications typical of each class.For parallel and heterogeneous systems, an estimation-theoreticredesign resulted in a 30%--40% power reduction in wireless andvideo systems.The application-awareness characteristic ofestimation-theoretic SoC design can also be adopted in designinggeneral-purpose processors. By exposing architectural diversity andcontrolled hardware errors in logic, the stochastic processor proposedhere allows dynamic power reduction of about 20%--60% in themotion-estimation block of a video communication system.In addressing power/reliability problems of general parallel SoCs, wehave also identified an important robust estimation problem that hasremained largely unaddressed within the robust statistics community.To address this need, new methods for robust estimation withcorrelated observations were developed that could be applicable tomore general estimation problems.