Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs

Field-programmable gate arrays;Power optimization;low-power design;logic synthesis;technology mapping;Electrical and Computer Engineering

Ravishankar, Chirag

University of Waterloo

关键词: Field-programmable gate arrays;    Power optimization;    low-power design;    logic synthesis;    technology mapping;    Electrical and Computer Engineering;   

Others  :  https://uwspace.uwaterloo.ca/bitstream/10012/6644/1/Ravishankar_Chirag.pdf

瑞士|英语

来源: UWSPACE Waterloo Institutional Repository

【 摘 要 】

Guarded evaluation is a power reduction technique that involvesidentifying sub-circuits (within a larger circuit) whose inputs can beheld constant (guarded) at specific times during circuit operation,thereby reducing switching activity and lowering dynamic power.Theconcept is rooted in the property that under certain conditions, somesignals within digital designs are not ;;observable;; at designoutputs, making the circuitry that generates such signals a candidatefor guarding.Guarded evaluation has been demonstrated successfullyfor custom ASICs; in this work, we apply the technique to FPGAs.InASICs, guarded evaluation entails adding additional hardware to thedesign, increasing silicon area and cost. Here, we apply the techniquein a way that imposes minimal area overhead by leveraging existingunused circuitry within the FPGA. The LUT functionality is modifiedto incorporate the guards and reduce toggle rates. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit;;s inputs can be held constant without impacting the largercircuit;;s functional correctness.We propose a simple solution tothis problem based on discovering gating inputs using ;;non-inverting paths;; and trimming inputs using ;;partial non-inverting paths;; in thecircuit;;s AND-Inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by as much as 32% for FPGAs with 6-LUT architectures and 25% for 4-LUT architectures, onaverage, and can reduce power consumption in the FPGA interconnect by29% for 6-LUTs and 27% for 4-LUTs. A clustered architecture with four LUTs to a cluster and ten LUTs to a cluster produced the best power reduction results.We implement guarded evaluation at various stages of the FPGA CAD flow and analyze the reductions. We implementthe algorithm as post technology mapping, post packing and post placement optimizations. Guarded Evaluationas a post technology mapping algorithm inserted the most number of guards and hence achieved the highest activityand interconnect reduction. However, guarding signals come with a cost of increased fanout and stress on routingresources. Packing and placement provides the algorithm with additional information of the circuit which is leveragedto insert high quality guards with minimal impact on routing. Experimental results show that post-packingand post-placement methods have comparable reductions to post-mapping with considerably lesser impact on the criticalpath delay and routability of the circuit.