We make a case for developing statistical error models of nanoscale circuits, employing these for designing robust systems, and engineeringerror-statistics to enhance the performance of various robust design techniques. A simple additive error model is presented for arithmetic computations. The proposed error model is shown to be a strong function of the architecture, and a weak function of theinput statistics, thus enabling a one-time off-line characterization similar to delay and power characterization done presently. In addition, we propose architectural diversity and scheduling diversity to engineer the occurrence of independent errors as required by robust system design techniques such as soft N-modular redundancy (NMR). Finally, we employ error statistics to develop soft dual-MR (DMR) and triple-MR (TMR) techniques for the adder operation and the filter design. All quantitative results are demonstrated in a commercial 45 nm CMOS process.
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Characterization and Engineering of Error Statistics for Reliable Computation