Hardware acceleration for sparse Fourier image reconstruction

Hardware Acceleration;Sparse Image Reconstruction;Field-Programmable Gate Array (FPGA);Reconfigurable Computing

Dinh, Quang S. ; Bresler ; Yoram

关键词: Hardware Acceleration;    Sparse Image Reconstruction;    Field-Programmable Gate Array (FPGA);    Reconfigurable Computing;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/16848/1_Dinh_Quang.pdf?sequence=2&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Several supercomputer vendors now offer reconfigurable computing (RC) systems, combining general-purpose processors with field-programmable gate arrays (FPGAs). The FPGAs can be configured as custom computing architectures for the computationally intensive parts of each application. In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining custom pipelined vector engines, so thatdifferent computations can be carried out without reconfiguration overhead. Actual runtime performance data show that we achieve up to 10 times speedup compared to the software-only version. The design is estimated to provide even more speedup on a next-generation RC platform.