Parallelizing SHA-1

IEICE Electronics Express

Youjip Won¹  Hu-ung Lee¹  Seongjing Lee¹  Jae-woon Kim¹ 

[1] Department of Computer and Software, Hanyang University

关键词: cryptography;    Field-Programmable Gate Array (FPGA);    hardware implementation;    hash functions;    Secure Hash Algorithm (SHA);   

DOI  :  10.1587/elex.12.20150371

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(28)In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8% over the pipeline architecture that is known to have nearly achieved the theoretical performance limit. We implemented our system on the Xilinx Virtex-6 FPGA and verified the operations by interfacing it with MicroBlaze soft processor core.

【 授权许可】

Unknown