FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition

Field-Programmable Gate Array (FPGA);Restricted Boltzmann Machine (RBM)

Xia, Tian

关键词: Field-Programmable Gate Array (FPGA);    Restricted Boltzmann Machine (RBM);   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/78800/XIA-THESIS-2015.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Despite the recent success of neural network in the researcheld, the num-ber of resulting applications for non-academic settings is very limited. Onesetback for its popularity is that neural networks are typically implementedas software running on a general-purpose processor. The time complexityof the software implementation is usually O(n2). As a result, neural net-works are inadequate to meet the scalability and performance requirementsfor commercial or industrial uses. Several research works have dealt withaccelerating neural networks on Field-Programmable Gate Arrays (FPGAs),particularly for Restricted Boltzmann Machines (RBMs) | a very popularand hardware-friendly neural network model. However, when using theirimplementations for handwriting recognition, there are two major setbacks.First, the implementations assume that the sizes of the neural networks aresymmetric, while the size of RBM model for handwriting recognition is infact highly asymmetric. Second, these implementations cannott a modelwith a visible layer larger than 512 nodes on a single FPGA. Thus, they arehighly ine cient when apply to handwriting recognition application.In this thesis, a new framework was proposed for an RBM with asymmetricweights optimizing for handwriting recognition. The framework is tested onan Altera Stratix IV GX(EP4SGX230KF40C2) FPGA running at 100 MHz.The resources support a complete RBM model of 784 by 10 nodes. Theexperimental results show the computational speed of 4 billion connection-update-per-second and a speed-up of 134 fold with I/O time and a speed-up of 161 fold without I/O time compared with an optimized MATLABimplementation running on a 2.50 GHz Intel processor. Compared withprevious works, our implementation is able to achieve a much higher speed-up while maintaining comparable resources used.