New PCM based FPGA architecture and graphene memory cell design

Phase change memory (PCM);Graphene;Field-Programmable Gate Array (FPGA);Memory;Lookup table (LUT)

Wei, Chunan ; Chen ; Deming

关键词: Phase change memory (PCM);    Graphene;    Field-Programmable Gate Array (FPGA);    Memory;    Lookup table (LUT);   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/49715/Chunan_Wei.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

In this work, we introduce a new look-up table (LUT) implementation using phase change memory (PCM) cells. Utilizing the fact that PCM cells store data using resistance values, unlike traditional memory cells, the memory cell we propose can store up to 2 bits per cell. This is achieved by controlling the 1T2R PCM cell resistances between the on resistance and the off resistance. Taking advantage of this property, a new LUT is designed that can either store two functions or a single function with an additional input. Thus the new design greatly improves FPGA logic density and reduces the area and timing cost. In order to access this new type of memory cell, a sense circuit is designed. We also propose a new hybrid architecture that uses LUTs with single and independent twin-outputs. The architecture is evaluated over delay and area with different LUT configurations. Experimental results show that on average 50 percent area reduction and 10 percent delay reduction can be achieved with the use of the new PCM based LUTs over SRAM based designs. Also, further savings can be achieved by incorporating hybrid architecture.Also, we introduce a new device design based on the SYMFET. This new type of device can be implemented to a memory cell utilizing the graphene sheet-to-sheet tunneling effect to store data. The SYMFET sheet-to-sheet tunneling can generate high current density when the Dirac points of graphene sheets are aligned; low current density is generated when Dirac points are not aligned. This new SYMFET memory has a GIGIG (graphene-insulator-graphene-insulator-graphene) structure. With this new type of device structure, a new mechanism for controlling data stored in the memory cell is introduced. Based on self-limiting tunneling, a third piece of graphene sheet is inserted in-between the source and drain graphene sheets serving as the tunneling current control mechanism. We also developed methods to calculate the on/off currents and gate potentials for this device.