Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies

Static random-access memory (SRAM);Embedded dynamic random-access memory (eDRAM);memory hierarchy;computer architecture;leakage;refresh power

Jain, Prabhat ; Torrellas ; Josep

关键词: Static random-access memory (SRAM);    Embedded dynamic random-access memory (eDRAM);    memory hierarchy;    computer architecture;    leakage;    refresh power;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/34585/Jain_Prabhat.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

As manycores use dynamic energy ever more efficiently, static power consumptionbecomes a major concern. In particular, in a large manycorerunning at a low voltage, leakage in on-chip memory modules contributessubstantially to the chip’s power draw. This is unfortunate given that, intuitively,the large multi-level cache hierarchy of a manycore is likely to containa lot of useless data.An effective way to reduce this problem is to use a low-leakage technologysuch as embedded DRAM (eDRAM). However, such systems requirerefresh. In this paper, we examine the opportunity of minimizing on-chipmemory power by intelligently refreshing a full-eDRAM cache hierarchy. Wepresent Refrint, a simple approach to perform fine-grained, intelligent refreshof eDRAM multiprocessor cache hierarchies. We introduce the Refrintalgorithms and the microarchitecture support. We evaluate Refrint in a simulatedmanycore running 16-threaded parallel applications. Compared toa full-SRAM system, Refrint’s memory hierarchy only consumes 36% of theSRAM’s memory hierarchy energy and induces a negligible slowdown. In contrast,a basic full-eDRAM memory hierarchy consumes 50% of the SRAM’smemory hierarchy energy and induces a slowdown of 18%.