Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory

Journal of Low Power Electronics and Applications

Luís Vitório Cargnini¹  Lionel Torres²  Raphael Martins Brum²  Sophiane Senni² 

[1] HGST Inc., 3403 Yerba Buena Road, San Jose, CA 95135, USA;LIRMM - UMR CNRS 5506 - University of Montpellier 2, 161 Rue Ada, Montpellier 34095, France; E-Mails:

关键词: semiconductors;    VLSI;    SoC;    memory;    non-volatile memory (NVM);    Magnetic random access memory (MRAM);    embedded systems;    memory hierarchy;   

DOI  :  10.3390/jlpea4030214

来源: mdpi

【 摘 要 】

Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM. We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC.

【 授权许可】

CC BY   
© 2014 by the authors; licensee MDPI, Basel, Switzerland.