Test Chip Design for Process Variation Characterization in 3D Integrated Circuits

3D;TSV;process variations;Electrical and Computer Engineering

O'Sullivan, Conor

University of Waterloo

关键词: 3D;    TSV;    process variations;    Electrical and Computer Engineering;   

Others  :  https://uwspace.uwaterloo.ca/bitstream/10012/7888/1/OSullivan_Conor.pdf

瑞士|英语

来源: UWSPACE Waterloo Institutional Repository

【 摘 要 】

A test chip design is presented for the characterization of process variations and ThroughSilicon Via (TSV) induced mechanical stress in 3D integrated circuits. The chip was de-signed, layed-out, and taped-out for fabrication in a 130nm Tezzaron/GlobalFoundriesprocess through CMC microsystems. The test chip takes advantage of the architectureof 3D ICs to split its test structure onto the two tiers of the 3D IC, achieving a devicearray density of 40.94 m2 per device. The design also has a high spatial resolution andmeasurementdelity compared to similar 2D variation characterization test structures.Background leakage subtraction and radialltering are two techniques that are ap-plied to the chip;;s measurements to reduce its error further for subthreshold device currentmeasurements and stress-induced mobility measurements, respectively. Experimental mea-surements are be taken from the chip using a custom PCB measurement setup once thechip has returned from fabrication.