3D Networks-on-Chip mapping targeting minimum signal TSVs

IEICE Electronics Express

Huaxi Gu³  Dongrui Fan¹  Yintang Yang²  Hui Ding³ 

[1] Key Laboratory of Computer System and Architecture Institute of Computing Technology, Chinese Academy of Sciences;Institute of Microelectronics, Xidian University;State Key Laboratory of ISN, Xidian University

关键词: Networks-on-Chip;    3D;    mapping;    TSV;   

DOI  :  10.1587/elex.10.20130518

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)The sharply increased complexity of multi-core systems has motivated the architecture of Networks-on-Chip (NoC) to evolve from 2D to 3D. With the objective of optimizing 3D NoC system for specific applications, a new mapping scheme with the goal of reducing signal TSVs and peak temperature is proposed in this paper. The inter-layer communication is optimized, which facilitates reduction of signal TSVs. What’s more, the peak temperature is limited by placing IP cores with high power on the layer close to the heat sink. Experimental results indicate that the number of signal TSVs is decreased and that tradeoffs can be made between the number of signal TSVs and peak temperature.

【 授权许可】

Unknown