Leakage Power Modeling and Reduction Techniques for Field Programmable Gate Arrays

Electrical & Computer Engineering;Leakage Power;FPGAs

Kumar, Akhilesh

University of Waterloo

关键词: Electrical & Computer Engineering;    Leakage Power;    FPGAs;   

Others  :  https://uwspace.uwaterloo.ca/bitstream/10012/766/1/a5kumar2006.pdf

瑞士|英语

来源: UWSPACE Waterloo Institutional Repository

【 摘 要 】

FPGAs have become quite popular for implementing digital circuits and systems becauseof reduced costs and fast design cycles. This has led to increased complexity ofFPGAs, and with technology scaling, many new challenges have come up for the FPGAindustry, leakage power being one of the key challenges. The current generation FPGAsare being implemented in 90nm technology, therefore, managing leakage power in deep-submicronFPGAs has become critical for the FPGA industry to remain competitive inthe semiconductor market and to enter the mobile applications domain.

In this work an analytical state dependent leakage power model for FPGAs is developed,followed by dual-Vt based designs of the FPGA architecture for reducing leakagepower.

The leakage power model computes subthreshold and gate leakage in FPGAs, sincethese are the two dominant components of total leakage power in the scaled nanometertechnologies. The leakage power model takes into account the dependency of gate andsubthreshold leakage on the state of the circuit inputs. The leakage power model has twomain components, one which computes the probability of a state for a particular FPGAcircuit element, and the other which computes the leakage of the FPGA circuit elementfor a given input using analytical equations. This FPGA power model is particularlyimportant for rapidly analyzing various FPGA architectures across different technologynodes.

Dual-Vt based designs of the FPGA architecture are proposed, developed, and evaluated,for reducing the leakage power using a CAD framework. The logic and the routingresources of the FPGA are considered for dual-Vt assignment. The number of the logicelements that can be assigned high-Vt in the ideal case by using a dual-Vt assignmentalgorithm in the CAD framework is estimated. Based upon this estimate two kinds of architecturesare developed and evaluated, homogeneous and heterogeneous architectures.Results indicate that leakage power savings of up to 50% can be obtained from thesearchitectures. The analytical state dependent leakage power model developed has beenused for estimating the leakage power savings from the dual-Vt FPGA architectures. TheCAD framework that has been developed can also be used for developing and evaluatingdifferent dual-Vt FPGA architectures, other than the ones proposed in this work.