Efficient Monte Carlo Based Methods for Variability Aware Analysis andOptimization of Digital Circuits.

Statistical Timing Analysis;Process Variability;Digital Circuits;Leakage Power;Monte Carlo;Electrical Engineering;Engineering;Electrical Engineering

Thazhathu Veetil, VineethSaigal, Romesh ;

University of Michigan

关键词: Statistical Timing Analysis;    Process Variability;    Digital Circuits;    Leakage Power;    Monte Carlo;    Electrical Engineering;    Engineering;    Electrical Engineering;   

Others  :  https://deepblue.lib.umich.edu/bitstream/handle/2027.42/78936/tvvin_1.pdf?sequence=1&isAllowed=y

瑞士|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Process variability is of increasing concern in modern nanometer-scale CMOS. Thesuitability of Monte Carlo based algorithms for efficient analysis and optimization ofdigital circuits under variability is explored in this work. Random sampling based MonteCarlo techniques incur high cost of computation, due to the large sample size required toachieve target accuracy. This motivates the need for intelligent sample selectiontechniques to reduce the number of samples. As these techniques depend on informationabout the system under analysis, there is a need to tailor the techniques to fit the specificapplication context. We propose efficient smart sampling based techniques for timing andleakage power consumption analysis of digital circuits. For the case of timing analysis, weshow that the proposed method requires 23.8X fewer samples on average to achievecomparable accuracy as a random sampling approach, for benchmark circuits studied. It isfurther illustrated that the parallelism available in such techniques can be exploited usingparallel machines, especially Graphics Processing Units. Here, we show that SH-QMCimplemented on a Multi GPU is twice as fast as a single STA on a CPU for benchmarkcircuits considered. Next we study the possibility of using such information fromstatistical analysis to optimize digital circuits under variability, for example to achieveminimum area on silicon though gate sizing while meeting a timing constraint. Thoughseveral techniques to optimize circuits have been proposed in literature, it is not clear howmuch gains are obtained in these approaches specifically through utilization of statisticalinformation. Therefore, an effective lower bound computation technique is proposed toenable efficient comparison of statistical design optimization techniques. It is shown thateven techniques which use only limited statistical information can achieve results towithin 10% of the proposed lower bound. We conclude that future optimization researchshould shift focus from use of more statistical information to achieving more efficiencyand parallelism to obtain speed ups.