Cache Design for a Hardware Accelerated Sparse Texture Storage System

Computer Science;texture mapping;cache;sparse texture

Yee, Wai Min

University of Waterloo

关键词: Computer Science;    texture mapping;    cache;    sparse texture;   

Others  :  https://uwspace.uwaterloo.ca/bitstream/10012/1197/1/wmyee2004.pdf

瑞士|英语

来源: UWSPACE Waterloo Institutional Repository

【 摘 要 】

Hardware texture mapping is essential for real-time rendering.Unfortunately the memory bandwidth and latency oftenbounds performance in current graphicsarchitectures.Bandwidth consumption can be reduced by compressing the texturemap or by using a cache.However, the way a texture map occupies memoryand how it is accessed affects the pattern of memory accesses,which in turn affects cache performance.Thus texture compression schemes andcache architectures must be designed in conjunction with each other. We define a sparse texture to be a texture where a substantial percentage of the texture is constant.Sparse textures are of interest as they occur often,and they are used as partsof more general texture compression schemes.We present a hardware compatible implementation ofsparse textures based on B-tree indexing and explore cache designsfor it.We demonstrate that it is possibleto have the bandwidth consumption and miss rate due to the texturedata alone scale with the area of the region of interest.We also show that the additionalbandwidth consumption and hideable latency due tothe B-tree indices are low.Furthermore, the caches necessary for these textures can be quite small.