Hybrid Designs for Caches and Cores.

microarchitecture;hybrid;in-order;out-of-order;way-prediction;cache;Computer Science;Engineering;Computer Science and Engineering

Sleiman, FaissalMahlke, Scott ;

University of Michigan

关键词: microarchitecture;    hybrid;    in-order;    out-of-order;    way-prediction;    cache;    Computer Science;    Engineering;    Computer Science and Engineering;   

Others  :  https://deepblue.lib.umich.edu/bitstream/handle/2027.42/113484/sleimanf_1.pdf?sequence=1&isAllowed=y

瑞士|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Processor power constraints have come to the forefront over the last decade, heralded by the stagnation of clock frequency scaling. High-performance core and cache designs often utilize power-hungry techniques to increase parallelism. Conversely, the most energy-efficient designs opt for a serial execution to avoid unnecessary overheads. While both of these extremes constitute one-size-fits-all approaches, a judicious mix of parallel and serial execution has the potential to achieve the best of both high-performing and energy-efficient designs. This dissertation examines such hybrid designs for cores and caches. Firstly, we introduce a novel, hybrid out-of-order/in-order core microarchitecture. Instructions that are steered towards in-order execution skip register allocation, reordering and dynamic scheduling. At the same time, these instructions can interleave on an instruction-by-instruction basis with instructions that continue to benefit from these conventional out-of-order mechanisms. Secondly, this dissertation revisits a hybrid technique introduced for L1 caches, way-prediction, in the context of last-level caches that are larger, have higher associativity, and experience less locality.