ADC and TDC Implemented Using FPGA.

Wu, J. ; Hansen, S. ; Shi, Z.

Technical Information Center Oak Ridge Tennessee

关键词: Front end electronics;    Stability;    Deserializer;    Implementation;    Algorithms;   

RP-ID  :  DE2008920719

学科分类：工程和技术（综合）

美国|英语

来源: National Technical Reports Library

【 摘 要 】

Several tests of FPGA devices programmed as analog waveform digitizers are discussed. The ADC uses the ramping-comparing scheme. A multi-channel ADC can be implemented with only a few resistors and capacitors as external components. A periodic logic levels are shaped by passive RC network to generate exponential ramps. The FPGA differential input buffers are used as comparators to compare the ramps with the input signals. The times at which these ramps cross the input signals are digitized by time-to-digital-converters (TDCs) implemented within the FPGA. The TDC portion of the logic alone has potentially a broad range of HEP/nuclear science applications. A 96-channel TDC card using FPGAs as TDCs being designed for the Fermilab MIPP electronics upgrade project is discussed. A deserializer circuit based on multisampling circuit used in the TDC, the Digital Phase Follower (DPF) is also documented.