FPGA Based 64-Bit Low Power RISCProcessor Using Verilog HDL

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

V.Prasanth¹  K.V.Rajeshkumar² 

[1] Department of ECE, Pragati Engineering College;Pragati Engineering College

关键词: RISC;    control unit;    processor;   

DOI  :  10.15662/ijareeie.2014.0311100

来源: Research & Reviews

【 摘 要 】

RISC is a design philosophy to reduce the complexity of instruction set that in turn reduces the amount of power consumption, space, cycle time, cost and other parameters taken into account during the implementation of the design. The advent of FPGA has enabled the complex logical systems to be implemented on FPGA. The intent of this paper is to design and implement 64 bit RISC processor using FPGA Spartan 3E tool. This processor design depends upon design specification, analysis and simulation. It takes into consideration very simple instruction set. The momentous components include Control unit, ALU, shift registers and accumulator register. Power consumption reduced by designing clocking techniques.

【 授权许可】

Unknown