Design and implementation of a floating point unit for rigel, a massively parallel accelerator

Floating point;Rigel;parallel;many core;multicore;processor;Accelerator;Floating point unit (FPU);floating point unit;IEEE Standard for Floating-Point Arithmetic (IEEE 754);Massively parallel

Truty, Wojciech J. ; Patel ; Sanjay J.

关键词: Floating point;    Rigel;    parallel;    many core;    multicore;    processor;    Accelerator;    Floating point unit (FPU);    floating point unit;    IEEE Standard for Floating-Point Arithmetic (IEEE 754);    Massively parallel;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/16472/Truty_Wojciech.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Scientific applications rely heavily on floating point data types. Floating point operationsare complex and require complicated hardware that is both area and power intensive. Theemergence of massively parallel architectures like Rigel creates new challenges and poses newquestions with respect to floating point support. The massively parallel aspect of Rigel places great emphasis on area efficient, low power designs. At the same time, Rigel is a generalpurpose accelerator and must provide high performance for a wide class of applications. Thisthesis presents an analysis of various floating point unit (FPU) components with respect toRigel, and attempts to present a candidate design of an FPU that balances performance,area, and power and is suitable for massively parallel architectures like Rigel.